Wednesday, April 23, 2008

Features of Define Macro in SystemVerilog

Following is the excerpt from SystemVerilog LRM about important features of define macro.

1. In Verilog, the ‘define macro text can include a backslash ( \ ) at the end of a line to show continuation on the next line.

2. In SystemVerilog, the macro text can also include `", `\`" and ``.
An `" overrides the usual lexical meaning of ", and indicates that the expansion should include an actual quotation mark. This allows string literals to be constructed from macro arguments.
A `\`" indicates that the expansion should include the escape sequence \", e.g.
`define msg(x,y) `"x: `\`"y`\`"`"
This expands:
$display(`msg(left side,right side));
$display("left side: \"right side\"");

3. A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments,

`define foo(f) f``_suffix
This expands:

These three are most important features because using them we can create customizable data_type and generic or reusable SystemVerilog Components.

For example consider following macro,
`define MY_DATA_TYPE(A) A
Using this macro, I can do following.

Instead of writing,
integer a;
I can write,
`MY_DATA_TYPE(integer) a;

You might think that is it advanced use of Macro? But when you read Reusable Channel using Define Macro of this article, you will realize that how this simple feature of define macro can help in creating generic/reusable components. Here, only intention is to convey that "Using define macro you can 'pass' data_type as argument".
define macro consider its argument as 'text only', it doesn't impose rule of 'keyword' or 'data type' on that. So passing data type as argument to define macro doesn't result into any compilation error.
These features can be used as an alternate option to 'Parameterization feature of SystemVerilog' (Parameterized Classes). If you are using EDA tool or SystemVerilog Compiler that doesn't support 'Parameterized class', you can use define macro as supplement for that, to make generic or reusable components.

Let's go through how to create generic/reusable SystemVerilog components using 'Parameterized Class' and Using 'Define Macro'.

Next: Reusable Channel using Parameterized class


  1. Please provide examples other than BOOK, which can provide something new for us.

  2. macro can be used as a guard against multiple compilation before and after the class
    statements. please give explanation to this statement.

  3. Go read the book Angel. Why stopping by here?

  4. Can I use define like this:
    `define type 1
    `define times 10
    `define cmd `times`type

    Actually I want to achieve :
    `cmd = 101 in binary so there should not be any gap in between two define values.